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Energy/area/delay trade-offs in the physical design of on-chip segmented buses architecture

dc.contributor.authorGuo, Jin
dc.contributor.authorPapanikolaou, Antonis
dc.contributor.authorHao, Zhang
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-16T16:25:51Z
dc.date.available2021-10-16T16:25:51Z
dc.date.issued2007-08
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12237
dc.sourceIIOimport
dc.titleEnergy/area/delay trade-offs in the physical design of on-chip segmented buses architecture
dc.typeJournal article
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage941
dc.source.endpage944
dc.source.journalIEEE Trans. on Very Large Scale Integration (VLSI) Systems
dc.source.issue8
dc.source.volume15
imec.availabilityPublished - imec


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