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Optimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example

dc.contributor.authorKanstein, Andreas
dc.contributor.authorLopez Suarez, Sebastian
dc.contributor.authorDe Sutter, Bjorn
dc.date.accessioned2021-10-16T17:02:30Z
dc.date.available2021-10-16T17:02:30Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12383
dc.sourceIIOimport
dc.titleOptimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example
dc.typeProceedings paper
dc.source.peerreviewno
dc.source.beginpage65900C
dc.source.conferenceVLSI Circuits and Systems III
dc.source.conferencedate2/05/2007
dc.source.conferencelocationMaspalomas Spain
imec.availabilityPublished - imec
imec.internalnotesProceedings of SPIE; Vol. 6590


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