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Sloped through wafer vias for 3D wafer level packaging

dc.contributor.authorSabuncuoglu Tezcan, Deniz
dc.contributor.authorPham, Nga
dc.contributor.authorMajeed, Bivragh
dc.contributor.authorBaert, Kris
dc.contributor.authorDe Moor, Piet
dc.contributor.authorRuythooren, Wouter
dc.date.accessioned2021-10-16T19:19:17Z
dc.date.available2021-10-16T19:19:17Z
dc.date.issued2007-05
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12829
dc.sourceIIOimport
dc.titleSloped through wafer vias for 3D wafer level packaging
dc.typeProceedings paper
dc.contributor.imecauthorSabuncuoglu Tezcan, Deniz
dc.contributor.imecauthorPham, Nga
dc.contributor.imecauthorMajeed, Bivragh
dc.contributor.imecauthorDe Moor, Piet
dc.contributor.imecauthorRuythooren, Wouter
dc.contributor.orcidimecSabuncuoglu Tezcan, Deniz::0000-0002-9237-7862
dc.source.peerreviewyes
dc.source.beginpage643
dc.source.endpage647
dc.source.conferenceProceedings 57th Electronic Components and Technology Conference - ECTC
dc.source.conferencedate29/05/2007
dc.source.conferencelocationReno, NV USA
imec.availabilityPublished - imec


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