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Scanning spreading resistance microscopy for the calibration of process simulators on 65nm MOS technology.

dc.contributor.authorVemula, Sri Charan
dc.contributor.authorEyben, Pierre
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorMody, Jay
dc.contributor.authorVandervorst, Wilfried
dc.date.accessioned2021-10-16T21:18:22Z
dc.date.available2021-10-16T21:18:22Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13159
dc.sourceIIOimport
dc.titleScanning spreading resistance microscopy for the calibration of process simulators on 65nm MOS technology.
dc.typeOral presentation
dc.contributor.imecauthorEyben, Pierre
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorVandervorst, Wilfried
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.source.peerreviewno
dc.source.conferenceInternational Workshop on INSIGHT in Semiconductor Device Fabrication, Metrology, and Modeling
dc.source.conferencedate6/05/2007
dc.source.conferencelocationNapa, CA USA
imec.availabilityPublished - imec


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