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A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM

dc.contributor.authorvon Arnim, Klaus
dc.contributor.authorAugendre, Emmanuel
dc.contributor.authorPacha, C.
dc.contributor.authorSchulz, Thomas
dc.contributor.authorSan, Kemal Tamer
dc.contributor.authorBauer, F.
dc.contributor.authorNackaerts, Axel
dc.contributor.authorRooyackers, Rita
dc.contributor.authorVandeweyer, Tom
dc.contributor.authorDegroote, Bart
dc.contributor.authorCollaert, Nadine
dc.contributor.authorDixit, Abhisek
dc.contributor.authorSinganamalla, Raghunath
dc.contributor.authorXiong, W.
dc.contributor.authorMarshall, A.
dc.contributor.authorCleavelin, C.R.
dc.contributor.authorSchrüfer, K.
dc.contributor.authorJurczak, Gosia
dc.date.accessioned2021-10-16T21:33:58Z
dc.date.available2021-10-16T21:33:58Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13200
dc.sourceIIOimport
dc.titleA low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
dc.typeProceedings paper
dc.contributor.imecauthorVandeweyer, Tom
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.source.peerreviewno
dc.source.beginpage106
dc.source.endpage107
dc.source.conferenceSymposium on VLSI Technology. Digest of Technical Papers
dc.source.conferencedate14/06/2007
dc.source.conferencelocationKyoto Japan
imec.availabilityPublished - imec


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