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Interconnect power analysis for a coarse-grained reconfigurable array processor

dc.contributor.authorBerekovic, Mladen
dc.contributor.authorBouwens, Frank
dc.contributor.authorVander Aa, Tom
dc.contributor.authorVerkest, Diederik
dc.date.accessioned2021-10-17T06:16:59Z
dc.date.available2021-10-17T06:16:59Z
dc.date.issued2008-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13371
dc.sourceIIOimport
dc.titleInterconnect power analysis for a coarse-grained reconfigurable array processor
dc.typeProceedings paper
dc.contributor.imecauthorVander Aa, Tom
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecVander Aa, Tom::0000-0002-1504-5266
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.source.peerreviewno
dc.source.conferenceInternational Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS
dc.source.conferencedate10/09/2008
dc.source.conferencelocationLisboa Portugal
imec.availabilityPublished - imec


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