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MOSART: Mapping Optimisation for Scalable multi-core ARchiTecture

dc.contributor.authorCandaele, Bernard
dc.contributor.authorJantsch, Axel
dc.contributor.authorAshby, Tom
dc.contributor.authorTiensyrjä, Kari
dc.contributor.authorIeromnimon, Frank
dc.contributor.authorVanthournout, Bart
dc.contributor.authorDi Crescenzo, Philippe
dc.contributor.authorSoudris, Dimitrios
dc.date.accessioned2021-10-17T06:25:59Z
dc.date.available2021-10-17T06:25:59Z
dc.date.issued2008
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13472
dc.sourceIIOimport
dc.titleMOSART: Mapping Optimisation for Scalable multi-core ARchiTecture
dc.typeProceedings paper
dc.contributor.imecauthorAshby, Tom
dc.source.peerreviewno
dc.source.beginpage343
dc.source.endpage344
dc.source.conference16th IFIP/IEEE International Conference on Very Large Scale Integration - VLSI-SoC
dc.source.conferencedate13/10/2008
dc.source.conferencelocationRhodes Greece
imec.availabilityPublished - imec
imec.internalnotesISBN 978-3-901882-32-6


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