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Mapping and design space exploration of the AES cryptographic algorithm on a coarse-grain reconfigurable array processor

dc.contributor.authorGarcia, Andres
dc.contributor.authorBerekovic, Mladen
dc.contributor.authorVander Aa, Tom
dc.date.accessioned2021-10-17T07:11:39Z
dc.date.available2021-10-17T07:11:39Z
dc.date.issued2008
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13750
dc.sourceIIOimport
dc.titleMapping and design space exploration of the AES cryptographic algorithm on a coarse-grain reconfigurable array processor
dc.typeProceedings paper
dc.contributor.imecauthorVander Aa, Tom
dc.contributor.orcidimecVander Aa, Tom::0000-0002-1504-5266
dc.source.peerreviewno
dc.source.beginpage251
dc.source.endpage256
dc.source.conference19th IEEE International Conference on Application-specific Systems, Architectures and Processors - ASAP
dc.source.conferencedate2/07/2008
dc.source.conferencelocationLeuven Belgium
imec.availabilityPublished - imec


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