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A tool flow for predicting system level timing failures due to interconnect reliability degradation

dc.contributor.authorGuo, Jin
dc.contributor.authorPapanikolaou, Antonis
dc.contributor.authorStucchi, Michele
dc.contributor.authorCroes, Kristof
dc.contributor.authorTokei, Zsolt
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-17T07:28:12Z
dc.date.available2021-10-17T07:28:12Z
dc.date.issued2008
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13824
dc.sourceIIOimport
dc.titleA tool flow for predicting system level timing failures due to interconnect reliability degradation
dc.typeProceedings paper
dc.contributor.imecauthorStucchi, Michele
dc.contributor.imecauthorCroes, Kristof
dc.contributor.imecauthorTokei, Zsolt
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCroes, Kristof::0000-0002-3955-0638
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage291
dc.source.endpage296
dc.source.conferenceProceedings 18th ACM Great Lakes Symposiun on VLSI
dc.source.conferencedate4/05/2008
dc.source.conferencelocationOrlando, FL USA
imec.availabilityPublished - open access


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