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Stochastic piecewise modeling of post-BD gate current oriented to circuit design

dc.contributor.authorMartin-Martinez, Javier
dc.contributor.authorKaczer, Ben
dc.contributor.authorAyala, N
dc.contributor.authorRodriguez, Rosana
dc.contributor.authorNafria, Montserrat
dc.contributor.authorAymerich, X
dc.contributor.authorZuber, Paul
dc.contributor.authorDierickx, Bart
dc.date.accessioned2021-10-17T08:52:18Z
dc.date.available2021-10-17T08:52:18Z
dc.date.issued2008
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14134
dc.sourceIIOimport
dc.titleStochastic piecewise modeling of post-BD gate current oriented to circuit design
dc.typeOral presentation
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorZuber, Paul
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.source.peerreviewno
dc.source.conferenceESSDERC Fringe Poster Session
dc.source.conferencedate15/09/2008
dc.source.conferencelocationEdinburgh UK
imec.availabilityPublished - imec


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