dc.contributor.author | Anchlia, Ankur | |
dc.contributor.author | Garcia Bardon, Marie | |
dc.contributor.author | Poliakov, Pavel | |
dc.contributor.author | Rooseleer, Bram | |
dc.contributor.author | De Wachter, Bart | |
dc.contributor.author | Collaert, Nadine | |
dc.contributor.author | van der Zanden, Koen | |
dc.contributor.author | Miranda Corbalan, Miguel | |
dc.contributor.author | Dehaene, Wim | |
dc.contributor.author | Verkest, Diederik | |
dc.date.accessioned | 2021-10-17T21:17:49Z | |
dc.date.available | 2021-10-17T21:17:49Z | |
dc.date.issued | 2009 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/14899 | |
dc.source | IIOimport | |
dc.title | Circuit design for bias compatibility investigation of bulk FinFET based floating body RAM | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Garcia Bardon, Marie | |
dc.contributor.imecauthor | Rooseleer, Bram | |
dc.contributor.imecauthor | De Wachter, Bart | |
dc.contributor.imecauthor | Collaert, Nadine | |
dc.contributor.imecauthor | Dehaene, Wim | |
dc.contributor.imecauthor | Verkest, Diederik | |
dc.contributor.orcidimec | Collaert, Nadine::0000-0002-8062-3165 | |
dc.contributor.orcidimec | Verkest, Diederik::0000-0001-6567-2746 | |
dc.source.peerreview | yes | |
dc.source.conference | IEEE Workshop on Memory Technology, Design and Testing | |
dc.source.conferencedate | 31/08/2009 | |
dc.source.conferencelocation | Hsinchu Taiwan | |
imec.availability | Published - imec | |