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Low-power reconfigurable network architecture for on-chip photonic interconnects

dc.contributor.authorArtundo, Inigo
dc.contributor.authorHeirman, Wim
dc.contributor.authorDebaes, Christof
dc.contributor.authorLoperena, Mikel
dc.contributor.authorVan Campenhout, Jan
dc.contributor.authorThienpont, Hugo
dc.date.accessioned2021-10-17T21:18:24Z
dc.date.available2021-10-17T21:18:24Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14915
dc.sourceIIOimport
dc.titleLow-power reconfigurable network architecture for on-chip photonic interconnects
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage163
dc.source.endpage169
dc.source.conferenceProceedings 17th IEEE Symposium on High Performance Interconnects
dc.source.conferencedate25/08/2009
dc.source.conferencelocationNew York USA
imec.availabilityPublished - open access


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