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Gate-level power analysis of on-chip communication infrastructures for biomedical applications

dc.contributor.authorBenjaminsen, Ruud
dc.contributor.authorDuarte, Filipa
dc.contributor.authorHuisken, Jos
dc.contributor.authorGoossens, Kees
dc.date.accessioned2021-10-17T21:21:54Z
dc.date.available2021-10-17T21:21:54Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14973
dc.sourceIIOimport
dc.titleGate-level power analysis of on-chip communication infrastructures for biomedical applications
dc.typeProceedings paper
dc.source.peerreviewyes
dc.source.conference20th Annual Workshop on Circuits, Systems and Signal Processing - ProRISC
dc.source.conferencedate26/11/2009
dc.source.conferencelocationVeldhoven The Netherlands
imec.availabilityPublished - imec


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