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3D IO interface design between memory and logic dies on TSV interconnects

dc.contributor.authorFacchini, Marco
dc.contributor.authorMarchal, Pol
dc.contributor.authorDehaene, Wim
dc.date.accessioned2021-10-17T22:10:05Z
dc.date.available2021-10-17T22:10:05Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15292
dc.sourceIIOimport
dc.title3D IO interface design between memory and logic dies on TSV interconnects
dc.typeProceedings paper
dc.contributor.imecauthorDehaene, Wim
dc.source.peerreviewyes
dc.source.conferenceHPCA-15 / Workshop on 3D Integration and Interconnection-Centric Architectures
dc.source.conferencedate14/02/2009
dc.source.conferencelocationRaleigh, NC USA
imec.availabilityPublished - imec


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