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Epitaxial Ge on standard STI patterned Si wafers: high quality virtual substrates for Ge pMOS and III/V nMOS

dc.contributor.authorLoo, Roger
dc.contributor.authorWang, Gang
dc.contributor.authorSouriau, Laurent
dc.contributor.authorLin, Vic
dc.contributor.authorTakeuchi, Shotaro
dc.contributor.authorBrammertz, Guy
dc.contributor.authorCaymax, Matty
dc.date.accessioned2021-10-18T00:11:30Z
dc.date.available2021-10-18T00:11:30Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15745
dc.sourceIIOimport
dc.titleEpitaxial Ge on standard STI patterned Si wafers: high quality virtual substrates for Ge pMOS and III/V nMOS
dc.typeProceedings paper
dc.contributor.imecauthorLoo, Roger
dc.contributor.imecauthorSouriau, Laurent
dc.contributor.imecauthorBrammertz, Guy
dc.contributor.imecauthorCaymax, Matty
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.contributor.orcidimecSouriau, Laurent::0000-0002-5138-5938
dc.contributor.orcidimecBrammertz, Guy::0000-0003-1404-7339
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage335
dc.source.endpage350
dc.source.conferenceULSI Process Integration 6
dc.source.conferencedate4/10/2009
dc.source.conferencelocationVienna Austria
imec.availabilityPublished - open access
imec.internalnotesECS Transactions; Vol. 25, Issue 7


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