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Testing 3D chips containing through-silicon vias

dc.contributor.authorMarinissen, Erik Jan
dc.contributor.authorZorian, Yervant
dc.date.accessioned2021-10-18T00:38:40Z
dc.date.available2021-10-18T00:38:40Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15833
dc.sourceIIOimport
dc.titleTesting 3D chips containing through-silicon vias
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.conferenceIEEE International Test Conference - ITC
dc.source.conferencedate1/11/2009
dc.source.conferencelocationAustin, TX USA
imec.availabilityPublished - imec


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