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Pathfinding: A design methodology for fast exploration and optimization of 3D-stacked integrated circuits

dc.contributor.authorMilojevic, Dragomir
dc.contributor.authorRadojcic, Riko
dc.contributor.authorCarpenter, R.
dc.contributor.authorMarchal, Pol
dc.contributor.authorVan der Plas, Geert
dc.date.accessioned2021-10-18T00:48:50Z
dc.date.available2021-10-18T00:48:50Z
dc.date.issued2009-10
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15863
dc.sourceIIOimport
dc.titlePathfinding: A design methodology for fast exploration and optimization of 3D-stacked integrated circuits
dc.typeProceedings paper
dc.contributor.imecauthorMilojevic, Dragomir
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.source.peerreviewno
dc.source.conferenceInternational Symposium System-on-Chip - SoC
dc.source.conferencedate7/10/2009
dc.source.conferencelocationTampere Finland
imec.availabilityPublished - imec


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