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Optimizing the FPGA memory design for a Sobel edge detector

dc.contributor.authorMoore, Graig Truett
dc.contributor.authorDevos, Harald
dc.contributor.authorStroobandt, Dirk
dc.date.accessioned2021-10-18T00:57:00Z
dc.date.available2021-10-18T00:57:00Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15887
dc.sourceIIOimport
dc.titleOptimizing the FPGA memory design for a Sobel edge detector
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage299
dc.source.endpage300
dc.source.conferenceEngineering of Reconfigurable Systems and Algorithms, Proceedings
dc.source.conferencedate13/07/2009
dc.source.conferencelocationLes Vegas, NV USA
imec.availabilityPublished - open access
imec.internalnotes


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