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Architecture exploration for digital decimation filters

dc.contributor.authorNovo Bruna, David
dc.contributor.authorFasthuber, Robert
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorBourdoux, André
dc.contributor.authorCatthoor, Francky
dc.contributor.authorVan der Perre, Liesbet
dc.date.accessioned2021-10-18T01:10:27Z
dc.date.available2021-10-18T01:10:27Z
dc.date.issued2009-11
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15926
dc.sourceIIOimport
dc.titleArchitecture exploration for digital decimation filters
dc.typeProceedings paper
dc.contributor.imecauthorBourdoux, André
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecBourdoux, André::0000-0002-9264-7850
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.conferenceProceedings of IEEE Workshop on Signal Processing Systems - SiPS
dc.source.conferencedate7/11/2009
dc.source.conferencelocationTampere Finland
imec.availabilityPublished - imec


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