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A 6-bit 50-MS/s hhreshold configuring SAR ADC in 90-nm digital CMOS

dc.contributor.authorNuzzo, Pierluigi
dc.contributor.authorNani, Claudio
dc.contributor.authorArmiento, Costantino
dc.contributor.authorSangiovanni-Vincentelli, Alberto
dc.contributor.authorCraninckx, Jan
dc.contributor.authorVan der Plas, Geert
dc.date.accessioned2021-10-18T01:12:07Z
dc.date.available2021-10-18T01:12:07Z
dc.date.issued2009-06
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15931
dc.sourceIIOimport
dc.titleA 6-bit 50-MS/s hhreshold configuring SAR ADC in 90-nm digital CMOS
dc.typeProceedings paper
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.source.peerreviewno
dc.source.beginpage238
dc.source.endpage239
dc.source.conferenceSymposium on VLSI Circuits
dc.source.conferencedate16/06/2009
dc.source.conferencelocationKyoto Japan
imec.availabilityPublished - imec


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