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Stress memorization technique – fundamental understanding and low-cost integration for advanced CMOS technology using a nonselective process

dc.contributor.authorOrtolland, Claude
dc.contributor.authorOkuno, Yasutoshi
dc.contributor.authorVerheyen, Peter
dc.contributor.authorKerner, Christoph
dc.contributor.authorStapelmann, Chris
dc.contributor.authorAoulaiche, Marc
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorHoffmann, Thomas Y.
dc.date.accessioned2021-10-18T01:18:52Z
dc.date.available2021-10-18T01:18:52Z
dc.date.issued2009
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/15950
dc.sourceIIOimport
dc.titleStress memorization technique – fundamental understanding and low-cost integration for advanced CMOS technology using a nonselective process
dc.typeJournal article
dc.contributor.imecauthorVerheyen, Peter
dc.contributor.imecauthorKerner, Christoph
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.contributor.orcidimecVerheyen, Peter::0000-0002-8245-9442
dc.source.peerreviewyes
dc.source.beginpage1690
dc.source.endpage1697
dc.source.journalIEEE Transactions on Electron Devices
dc.source.issue8
dc.source.volume56
imec.availabilityPublished - imec


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