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A 57-66 GHz PLL in 45 nm digital CMOS

dc.contributor.authorScheir, Karen
dc.contributor.authorVandersteen, Gerd
dc.contributor.authorRolain, Yves
dc.contributor.authorWambacq, Piet
dc.date.accessioned2021-10-18T02:40:40Z
dc.date.available2021-10-18T02:40:40Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16168
dc.sourceIIOimport
dc.titleA 57-66 GHz PLL in 45 nm digital CMOS
dc.typeProceedings paper
dc.contributor.imecauthorVandersteen, Gerd
dc.contributor.imecauthorWambacq, Piet
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage494
dc.source.endpage495
dc.source.conferenceIEEE International Solid-State Circuits Conference - ISSCC
dc.source.conferencedate8/02/2009
dc.source.conferencelocationSan Fransisco, CA USA
imec.availabilityPublished - open access


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