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Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors

dc.contributor.authorTaniguchi, Ittetsu
dc.contributor.authorJayapala, Murali
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorCatthoor, Francky
dc.contributor.authorTakeuchi, Yoshinori
dc.contributor.authorImai, Masaharu
dc.date.accessioned2021-10-18T03:30:16Z
dc.date.available2021-10-18T03:30:16Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16290
dc.sourceIIOimport
dc.titleSystematic architecture exploration based on optimistic cycle estimation for low energy embedded processors
dc.typeProceedings paper
dc.contributor.imecauthorJayapala, Murali
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecJayapala, Murali::0000-0001-7917-0149
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage449
dc.source.endpage454
dc.source.conferenceAsia and South Pacific Design Automation Conference - ASPDAC
dc.source.conferencedate19/01/2009
dc.source.conferencelocationYokohoma Japan
imec.availabilityPublished - open access


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