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Design space exploration of all-digital symbol timing adjustment architectures

dc.contributor.authorVernalde, Serge
dc.contributor.authorSchaumont, Patrick
dc.contributor.authorEngels, Marc
dc.contributor.authorBolsens, Ivo
dc.date.accessioned2021-09-29T15:49:31Z
dc.date.available2021-09-29T15:49:31Z
dc.date.issued1996
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/1637
dc.sourceIIOimport
dc.titleDesign space exploration of all-digital symbol timing adjustment architectures
dc.typeProceedings paper
dc.contributor.imecauthorVernalde, Serge
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage88
dc.source.endpage93
dc.source.conferenceProceedings IEEE 4th Symposium on Communications and Vehicular Technology in the Benelux
dc.source.conferencedate7/10/1996
dc.source.conferencelocationGent Belgium
imec.availabilityPublished - open access


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