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Analysis of fractional spur reduction using SD noise cancellation in digital PLL

dc.contributor.authorVengattaramane, Kameswaran
dc.contributor.authorCraninckx, Jan
dc.contributor.authorSteyaert, Michiel
dc.date.accessioned2021-10-18T04:39:25Z
dc.date.available2021-10-18T04:39:25Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16456
dc.sourceIIOimport
dc.titleAnalysis of fractional spur reduction using SD noise cancellation in digital PLL
dc.typeProceedings paper
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage2397
dc.source.endpage2400
dc.source.conferenceIEEE International Conference on Circuits and Systems - ISCAS
dc.source.conferencedate24/05/2009
dc.source.conferencelocationTaipei Taiwan
imec.availabilityPublished - open access


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