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Design and synthesis of Pareto buffers offering large range runtime energy/delay trade-offs via combined buffer size and supply voltage tuning

dc.contributor.authorWang, Hua
dc.contributor.authorMiranda Corbalan, Miguel
dc.contributor.authorDehaene, Wim
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-18T05:07:32Z
dc.date.available2021-10-18T05:07:32Z
dc.date.issued2009
dc.identifier.issn1063-8210
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16520
dc.sourceIIOimport
dc.titleDesign and synthesis of Pareto buffers offering large range runtime energy/delay trade-offs via combined buffer size and supply voltage tuning
dc.typeJournal article
dc.contributor.imecauthorDehaene, Wim
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewyes
dc.source.beginpage117
dc.source.endpage127
dc.source.journalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.source.issue1
dc.source.volume17
imec.availabilityPublished - imec


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