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Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures

dc.contributor.authorBenbakhti, Brahim
dc.contributor.authorAyubi-Moak, J.S.
dc.contributor.authorKalna, Karol
dc.contributor.authorLin, Dennis
dc.contributor.authorHellings, Geert
dc.contributor.authorBrammertz, Guy
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorThayne, I.
dc.contributor.authorAsenov, Asen
dc.date.accessioned2021-10-18T15:19:51Z
dc.date.available2021-10-18T15:19:51Z
dc.date.issued2010
dc.identifier.issn0026-2714
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16730
dc.sourceIIOimport
dc.titleImpact of interface state trap density on the performance characteristics of different III-V MOSFET architectures
dc.typeJournal article
dc.contributor.imecauthorLin, Dennis
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorBrammertz, Guy
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecBrammertz, Guy::0000-0003-1404-7339
dc.source.peerreviewyes
dc.source.beginpage360
dc.source.endpage364
dc.source.journalMicroelectronics Reliability
dc.source.issue3
dc.source.volume50
dc.identifier.urlhttp://dx.doi.org/10.1016/j.mee.2009.03.024
imec.availabilityPublished - imec


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