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A parallel method for functional verification of medium and high throughput DSP synthesis

dc.contributor.authorGenoe, Mark
dc.contributor.authorClaesen, Luc
dc.contributor.authorDe Man, Hugo
dc.date.accessioned2021-09-29T12:41:33Z
dc.date.available2021-09-29T12:41:33Z
dc.date.issued1994
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/169
dc.sourceIIOimport
dc.titleA parallel method for functional verification of medium and high throughput DSP synthesis
dc.typeProceedings paper
dc.contributor.imecauthorDe Man, Hugo
dc.source.peerreviewno
dc.source.beginpage460
dc.source.endpage463
dc.source.conferenceIEEE International Conference on Computer Design : VLSI in Computers and Processors - ICCD
dc.source.conferencedate10/10/1994
dc.source.conferencelocationCambridge, Ma USA
imec.availabilityPublished - imec


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