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Capacitance reduction technique for through silicon via (TSV) in p-Si substrate

dc.contributor.authorKatti, Guruprasad
dc.contributor.authorStucchi, Michele
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorDehaene, Wim
dc.date.accessioned2021-10-18T17:33:40Z
dc.date.available2021-10-18T17:33:40Z
dc.date.issued2010
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17355
dc.sourceIIOimport
dc.titleCapacitance reduction technique for through silicon via (TSV) in p-Si substrate
dc.typeJournal article
dc.contributor.imecauthorStucchi, Michele
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.imecauthorDehaene, Wim
dc.source.peerreviewyes
dc.source.beginpage549
dc.source.endpage551
dc.source.journalIEEE Electron Device Letters
dc.source.issue6
dc.source.volume31
imec.availabilityPublished - imec


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