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Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions

dc.contributor.authorLeonelli, Daniele
dc.contributor.authorVandooren, Anne
dc.contributor.authorRooyackers, Rita
dc.contributor.authorDe Gendt, Stefan
dc.contributor.authorHeyns, Marc
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-18T18:09:33Z
dc.date.available2021-10-18T18:09:33Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17468
dc.sourceIIOimport
dc.titleOptimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions
dc.typeProceedings paper
dc.contributor.imecauthorLeonelli, Daniele
dc.contributor.imecauthorVandooren, Anne
dc.contributor.imecauthorDe Gendt, Stefan
dc.contributor.imecauthorHeyns, Marc
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecVandooren, Anne::0000-0002-2412-0176
dc.contributor.orcidimecDe Gendt, Stefan::0000-0003-3775-3578
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage170
dc.source.endpage173
dc.source.conference40th European Solid-State Device Research Conference - ESSDERC
dc.source.conferencedate13/09/2010
dc.source.conferencelocationSevilla Spain
imec.availabilityPublished - open access


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