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Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

dc.contributor.authorBock, Karlheinz
dc.contributor.authorRuss, Christian
dc.contributor.authorBadenes, Gonçal
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorDeferm, Ludo
dc.date.accessioned2021-09-30T07:57:56Z
dc.date.available2021-09-30T07:57:56Z
dc.date.issued1997
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/1748
dc.sourceIIOimport
dc.titleInfluence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology
dc.typeProceedings paper
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.imecauthorDeferm, Ludo
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage308
dc.source.endpage315
dc.source.conferenceElectrical Overstress/ Electrostatic Discharge Symposium
dc.source.conferencedate23/09/1997
dc.source.conferencelocationSanta Clara, CA USA
imec.availabilityPublished - imec


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