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200 nm wafer scale III-V/SOI technology for all-optical network-on-chip and signal processing

dc.contributor.authorLiu, Liu
dc.contributor.authorSpuesens, Thijs
dc.contributor.authorVan Thourhout, Dries
dc.contributor.authorMorthier, Geert
dc.contributor.authorGrenouillet, Laurent
dc.contributor.authorOlivier, Nicolas
dc.contributor.authorFedeli, J.M.
dc.contributor.authorRojo-Romeo, Pedro
dc.contributor.authorRegreny, Philippe
dc.contributor.authorMandorlo, Fabien
dc.contributor.authorOrobtchouk, Regis
dc.date.accessioned2021-10-18T18:25:23Z
dc.date.available2021-10-18T18:25:23Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17514
dc.sourceIIOimport
dc.title200 nm wafer scale III-V/SOI technology for all-optical network-on-chip and signal processing
dc.typeProceedings paper
dc.contributor.imecauthorVan Thourhout, Dries
dc.contributor.imecauthorMorthier, Geert
dc.contributor.orcidimecVan Thourhout, Dries::0000-0003-0111-431X
dc.contributor.orcidimecMorthier, Geert::0000-0003-1819-6489
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage7
dc.source.endpage9
dc.source.conference7th IEEE International Conference on Group IV Photonics
dc.source.conferencedate1/09/2010
dc.source.conferencelocationBeijing China
imec.availabilityPublished - open access


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