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Challenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access

dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-18T18:49:32Z
dc.date.available2021-10-18T18:49:32Z
dc.date.issued2010-12
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17581
dc.sourceIIOimport
dc.titleChallenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage544
dc.source.endpage547
dc.source.conferenceIEEE Asia Pacific Conference on Circuits and Systems - APCCAS
dc.source.conferencedate6/12/2010
dc.source.conferencelocationKuala Lumpur Malaysia
imec.availabilityPublished - imec


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