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Die-wrapper optimization for 3D stacked ICs

dc.contributor.authorNoia, Brandon
dc.contributor.authorChakrabarty, Krishnendu
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-18T19:39:10Z
dc.date.available2021-10-18T19:39:10Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17706
dc.sourceIIOimport
dc.titleDie-wrapper optimization for 3D stacked ICs
dc.typeOral presentation
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewno
dc.source.conferenceIEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits - 3D-TEST
dc.source.conferencedate4/11/2010
dc.source.conferencelocationAustin, TX USA
imec.availabilityPublished - imec


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