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Reduction of circuit complexity using tensor analysis of networks

dc.contributor.authorCoen, G.
dc.contributor.authorDe Zutter, Daniel
dc.date.accessioned2021-09-30T08:01:16Z
dc.date.available2021-09-30T08:01:16Z
dc.date.issued1997
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/1778
dc.sourceIIOimport
dc.titleReduction of circuit complexity using tensor analysis of networks
dc.typeProceedings paper
dc.contributor.imecauthorDe Zutter, Daniel
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage535
dc.source.endpage540
dc.source.conferenceProceedings of the 12th International Zürich Symposium and Technical Exhibition on Electromagnetic Compatibility
dc.source.conferencedate18/02/1997
dc.source.conferencelocationZürich Swizerland
imec.availabilityPublished - imec


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