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Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing

dc.contributor.authorSathanur, Ashoka
dc.contributor.authorAshouei, Maryam
dc.contributor.authorHuisken, Jos
dc.date.accessioned2021-10-18T21:19:17Z
dc.date.available2021-10-18T21:19:17Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17952
dc.sourceIIOimport
dc.titleImproving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage178
dc.source.endpage181
dc.source.conferenceInternational Conference on Integrated Circuit Design and Technology - ICIDT
dc.source.conferencedate2/06/2010
dc.source.conferencelocationGrenoble France
imec.availabilityPublished - open access


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