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Methodology for design optimization of SOI FinFET grounded-gate NMOS devices

dc.contributor.authorThijs, Steven
dc.contributor.authorRuss, Christian
dc.contributor.authorTremouilles, David
dc.contributor.authorGriffoni, Alessio
dc.contributor.authorLinten, Dimitri
dc.contributor.authorScholz, Mirko
dc.contributor.authorCollaert, Nadine
dc.contributor.authorRooyackers, Rita
dc.contributor.authorJurczak, Gosia
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-18T22:18:39Z
dc.date.available2021-10-18T22:18:39Z
dc.date.issued2010
dc.identifier.issn1530-4388
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18082
dc.sourceIIOimport
dc.titleMethodology for design optimization of SOI FinFET grounded-gate NMOS devices
dc.typeJournal article
dc.contributor.imecauthorThijs, Steven
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecThijs, Steven::0000-0003-2889-8345
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage338
dc.source.endpage346
dc.source.journalIEEE Transactions on Device and Materials Reliability
dc.source.issue3
dc.source.volume10
imec.availabilityPublished - open access


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