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Micro-architectural optimization of a coarse-crained array based baseband processor

dc.contributor.authorVander Aa, Tom
dc.contributor.authorHartmann, Matthias
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorDejonghe, Antoine
dc.contributor.authorVan der Perre, Liesbet
dc.date.accessioned2021-10-18T23:21:15Z
dc.date.available2021-10-18T23:21:15Z
dc.date.issued2010-10
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18217
dc.sourceIIOimport
dc.titleMicro-architectural optimization of a coarse-crained array based baseband processor
dc.typeProceedings paper
dc.contributor.imecauthorVander Aa, Tom
dc.contributor.imecauthorHartmann, Matthias
dc.contributor.orcidimecVander Aa, Tom::0000-0002-1504-5266
dc.contributor.orcidimecHartmann, Matthias::0000-0001-6248-1151
dc.source.peerreviewno
dc.source.conferenceIEEE Workshop on Signal Processing Systems - SiPS
dc.source.conferencedate6/10/2010
dc.source.conferencelocationCupertino, CA USA
imec.availabilityPublished - imec


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