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Joint-optimization for SRAM and Logic for 28nm node and below

dc.contributor.authorVerhaegen, Staf
dc.contributor.authorSmayling, Michael C.
dc.contributor.authorDe Bisschop, Peter
dc.contributor.authorLaenens, Bart
dc.date.accessioned2021-10-18T23:47:21Z
dc.date.available2021-10-18T23:47:21Z
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18273
dc.sourceIIOimport
dc.titleJoint-optimization for SRAM and Logic for 28nm node and below
dc.typeProceedings paper
dc.contributor.imecauthorDe Bisschop, Peter
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage764107
dc.source.conferenceDesign for Manufacturability through Design-Process Integration IV
dc.source.conferencedate21/02/2010
dc.source.conferencelocationSan Jose, CA USA
imec.availabilityPublished - open access
imec.internalnotesProceedings SPIE; Vol.7641


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