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Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

dc.contributor.authorYang, Yu
dc.contributor.authorLabie, Riet
dc.contributor.authorLing, Fangzhou
dc.contributor.authorZhao, Chao
dc.contributor.authorRadisic, Alex
dc.contributor.authorVan Olmen, Jan
dc.contributor.authorTravaly, Youssef
dc.contributor.authorVerlinden, Bert
dc.contributor.authorDe Wolf, Ingrid
dc.date.accessioned2021-10-19T00:41:47Z
dc.date.available2021-10-19T00:41:47Z
dc.date.issued2010
dc.identifier.issn0026-2714
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18381
dc.sourceIIOimport
dc.titleProcessing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures
dc.typeJournal article
dc.contributor.imecauthorLabie, Riet
dc.contributor.imecauthorRadisic, Alex
dc.contributor.imecauthorVan Olmen, Jan
dc.contributor.imecauthorDe Wolf, Ingrid
dc.contributor.orcidimecLabie, Riet::0000-0002-1401-1291
dc.contributor.orcidimecDe Wolf, Ingrid::0000-0003-3822-5953
dc.source.peerreviewyes
dc.source.beginpage1636
dc.source.endpage1640
dc.source.journalMicroelectronics Reliability
dc.source.issue9_11
dc.source.volume50
dc.identifier.urlhttp://dx.doi.org/10.1016/j.microrel.2010.07.019
imec.availabilityPublished - imec
imec.internalnotesESREF 2010 paper


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