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Relation between trap creation and breakdown during tunnelling current stressing of sub 3nm gate oxide

dc.contributor.authorDepas, Michel
dc.contributor.authorHeyns, Marc
dc.date.accessioned2021-09-30T08:11:43Z
dc.date.available2021-09-30T08:11:43Z
dc.date.issued1997
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/1852
dc.sourceIIOimport
dc.titleRelation between trap creation and breakdown during tunnelling current stressing of sub 3nm gate oxide
dc.typeJournal article
dc.contributor.imecauthorHeyns, Marc
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage21
dc.source.endpage24
dc.source.journalMicroelectronic Engineering
dc.source.volume36
imec.availabilityPublished - open access


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