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3D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias

dc.contributor.authorCivale, Yann
dc.contributor.authorSabuncuoglu Tezcan, Deniz
dc.contributor.authorPhilipsen, Harold
dc.contributor.authorDuval, Fabrice
dc.contributor.authorJaenen, Patrick
dc.contributor.authorTravaly, Youssef
dc.contributor.authorSoussan, Philippe
dc.contributor.authorSwinnen, Bart
dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-19T12:51:15Z
dc.date.available2021-10-19T12:51:15Z
dc.date.issued2011
dc.identifier.issn2156-3950
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18702
dc.sourceIIOimport
dc.title3D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias
dc.typeJournal article
dc.contributor.imecauthorSabuncuoglu Tezcan, Deniz
dc.contributor.imecauthorPhilipsen, Harold
dc.contributor.imecauthorDuval, Fabrice
dc.contributor.imecauthorJaenen, Patrick
dc.contributor.imecauthorSoussan, Philippe
dc.contributor.imecauthorSwinnen, Bart
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecSabuncuoglu Tezcan, Deniz::0000-0002-9237-7862
dc.contributor.orcidimecPhilipsen, Harold::0000-0002-5029-1104
dc.contributor.orcidimecSoussan, Philippe::0000-0002-1347-6978
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage833
dc.source.endpage840
dc.source.journalIEEE Transactions on Components, Packaging and Manufacturing Technology
dc.source.issue6
dc.source.volume1
imec.availabilityPublished - open access


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