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Optimizing i-line lithography for 0.3-μm poly-gate manufacturing

dc.contributor.authorFinders, Jo
dc.contributor.authorTzviatkov, Plamen
dc.contributor.authorRonse, Kurt
dc.contributor.authorVan den hove, Luc
dc.date.accessioned2021-09-30T08:17:00Z
dc.date.available2021-09-30T08:17:00Z
dc.date.issued1997
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/1883
dc.sourceIIOimport
dc.titleOptimizing i-line lithography for 0.3-μm poly-gate manufacturing
dc.typeJournal article
dc.contributor.imecauthorRonse, Kurt
dc.contributor.imecauthorVan den hove, Luc
dc.contributor.orcidimecRonse, Kurt::0000-0003-0803-4267
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpageS5
dc.source.endpageS14
dc.source.journalSolid State Technology
dc.source.issueMarch
dc.source.volume40
imec.availabilityPublished - imec


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