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Automated design-for-test for 2.5D and 3D SICs

dc.contributor.authorMarinissen, Erik Jan
dc.contributor.authorKonijnenburg, Mario
dc.contributor.authorDeutsch, Sergej
dc.contributor.authorKeller, Brion
dc.contributor.authorChickermane, Vivek
dc.contributor.authorMukherjee, Subhasish
dc.contributor.authorGoel, Sandeep K.
dc.date.accessioned2021-10-19T16:04:46Z
dc.date.available2021-10-19T16:04:46Z
dc.date.issued2011-09
dc.identifier.issn1526-1344
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19389
dc.sourceIIOimport
dc.titleAutomated design-for-test for 2.5D and 3D SICs
dc.typeJournal article
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.imecauthorKonijnenburg, Mario
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.contributor.orcidimecKonijnenburg, Mario::0000-0001-8016-0888
dc.source.peerreviewno
dc.source.beginpage18
dc.source.endpage22
dc.source.journalChip Scale Review
dc.source.issue5
dc.source.volume?
dc.identifier.urlhttp://www.chipscalereview.com/issues/0911/
imec.availabilityPublished - imec


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