Feasibility study of Mo/SiOx/Pt resistive random access memory in inverter circuit for FPGA applications
dc.contributor.author | Park, Sangsu | |
dc.contributor.author | Shin, Jungho | |
dc.contributor.author | Cimino, Salvatore | |
dc.contributor.author | Jung, Seungjae | |
dc.contributor.author | Lee, Joonmyoung | |
dc.contributor.author | Kim, Seonghyun | |
dc.contributor.author | Park, Jubong | |
dc.contributor.author | Lee, Wootae | |
dc.contributor.author | Son, Myungwoo | |
dc.contributor.author | Lee, Byunghun | |
dc.contributor.author | Pantisano, Luigi | |
dc.contributor.author | Hwang, Hyngsang | |
dc.date.accessioned | 2021-10-19T17:06:06Z | |
dc.date.available | 2021-10-19T17:06:06Z | |
dc.date.issued | 2011 | |
dc.identifier.issn | 0741-3106 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/19540 | |
dc.source | IIOimport | |
dc.title | Feasibility study of Mo/SiOx/Pt resistive random access memory in inverter circuit for FPGA applications | |
dc.type | Journal article | |
dc.date.embargo | 9999-12-31 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 1665 | |
dc.source.endpage | 1667 | |
dc.source.journal | IEEE Electron Device Letters | |
dc.source.issue | 12 | |
dc.source.volume | 32 | |
imec.availability | Published - open access |