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Feasibility study of Mo/SiOx/Pt resistive random access memory in inverter circuit for FPGA applications

dc.contributor.authorPark, Sangsu
dc.contributor.authorShin, Jungho
dc.contributor.authorCimino, Salvatore
dc.contributor.authorJung, Seungjae
dc.contributor.authorLee, Joonmyoung
dc.contributor.authorKim, Seonghyun
dc.contributor.authorPark, Jubong
dc.contributor.authorLee, Wootae
dc.contributor.authorSon, Myungwoo
dc.contributor.authorLee, Byunghun
dc.contributor.authorPantisano, Luigi
dc.contributor.authorHwang, Hyngsang
dc.date.accessioned2021-10-19T17:06:06Z
dc.date.available2021-10-19T17:06:06Z
dc.date.issued2011
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19540
dc.sourceIIOimport
dc.titleFeasibility study of Mo/SiOx/Pt resistive random access memory in inverter circuit for FPGA applications
dc.typeJournal article
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1665
dc.source.endpage1667
dc.source.journalIEEE Electron Device Letters
dc.source.issue12
dc.source.volume32
imec.availabilityPublished - open access


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