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dc.contributor.authorPawlak, Malgorzata
dc.contributor.authorKaczer, Ben
dc.contributor.authorWang, Wan-Chih
dc.contributor.authorKim, Min-Soo
dc.contributor.authorPopovici, Mihaela Ioana
dc.contributor.authorSwerts, Johan
dc.contributor.authorTomida, Kazuyuki
dc.contributor.authorOpsomer, Karl
dc.contributor.authorSchaekers, Marc
dc.contributor.authorVrancken, Christa
dc.contributor.authorGovoreanu, Bogdan
dc.contributor.authorBelmonte, Attilio
dc.contributor.authorDemeurisse, Caroline
dc.contributor.authorDebusschere, Ingrid
dc.contributor.authorAltimime, Laith
dc.contributor.authorAfanasiev, Valeri
dc.contributor.authorKittl, Jorge
dc.date.accessioned2021-10-19T17:11:52Z
dc.date.available2021-10-19T17:11:52Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19554
dc.sourceIIOimport
dc.titleTowards 1X DRAM: Improved leakage 0.4 nm EOT STO-based MIMcap and explanation of leakage reduction mechanism showing further potential
dc.typeProceedings paper
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorKim, Min-Soo
dc.contributor.imecauthorPopovici, Mihaela Ioana
dc.contributor.imecauthorSwerts, Johan
dc.contributor.imecauthorTomida, Kazuyuki
dc.contributor.imecauthorOpsomer, Karl
dc.contributor.imecauthorSchaekers, Marc
dc.contributor.imecauthorVrancken, Christa
dc.contributor.imecauthorGovoreanu, Bogdan
dc.contributor.imecauthorBelmonte, Attilio
dc.contributor.imecauthorDemeurisse, Caroline
dc.contributor.imecauthorDebusschere, Ingrid
dc.contributor.imecauthorAfanasiev, Valeri
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecKim, Min-Soo::0000-0003-0211-0847
dc.contributor.orcidimecSchaekers, Marc::0000-0002-1496-7816
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage168
dc.source.endpage169
dc.source.conferenceSymposium on VLSI Technology
dc.source.conferencedate13/06/2011
dc.source.conferencelocationKyoto Japan
imec.availabilityPublished - open access


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