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Impact of DRAM process flow on the performance of periphery devices for next generation mobile applications

dc.contributor.authorSpessot, Alessio
dc.contributor.authorCaillat, Christian
dc.contributor.authorSrividya, Vidya
dc.contributor.authorFazan, Pierre
dc.contributor.authorSchram, Tom
dc.contributor.authorMitard, Jerome
dc.date.accessioned2021-10-19T19:07:03Z
dc.date.available2021-10-19T19:07:03Z
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19818
dc.sourceIIOimport
dc.titleImpact of DRAM process flow on the performance of periphery devices for next generation mobile applications
dc.typeProceedings paper
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorFazan, Pierre
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorMitard, Jerome
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecMitard, Jerome::0000-0002-7422-079X
dc.source.peerreviewyes
dc.source.conference2nd International Workshop on Simulation and Modeling of Memory - IWSM2
dc.source.conferencedate6/10/2011
dc.source.conferencelocationAgrate Brianza Italy
imec.availabilityPublished - imec


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