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How significant will be the test cost share for 3D die-to-wafer stacked ICs?

dc.contributor.authorTaouil, Mottaqiallah
dc.contributor.authorHamdioui, Said
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-19T19:31:23Z
dc.date.available2021-10-19T19:31:23Z
dc.date.issued2011-04
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19869
dc.sourceIIOimport
dc.titleHow significant will be the test cost share for 3D die-to-wafer stacked ICs?
dc.typeProceedings paper
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.conferenceIEEE 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era - DTIS
dc.source.conferencedate6/04/2011
dc.source.conferencelocationAthens Greece
dc.identifier.urlhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5941432
imec.availabilityPublished - imec


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