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Multi-gate fin field-effect transistors junctions optimization by conventional ion implantation for (Sub-)22 nm technology nodes circuit applications

dc.contributor.authorVeloso, Anabela
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorBrus, Stephan
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorAbsil, Philippe
dc.contributor.authorHoffmann, Thomas Y.
dc.date.accessioned2021-10-19T20:55:09Z
dc.date.available2021-10-19T20:55:09Z
dc.date.issued2011
dc.identifier.issn0021-4922
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20046
dc.sourceIIOimport
dc.titleMulti-gate fin field-effect transistors junctions optimization by conventional ion implantation for (Sub-)22 nm technology nodes circuit applications
dc.typeJournal article
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorBrus, Stephan
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorAbsil, Philippe
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.source.peerreviewyes
dc.source.beginpage04DC16-1
dc.source.journalJapanese Journal of Applied Physics
dc.source.issue4
dc.source.volume50
dc.identifier.urlhttp://jjap.jsap.jp/link?JJAP/50/04DC16/
imec.availabilityPublished - imec


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