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Utilizing Keep-Out Zone (KOZ) of Through Silicon Via (TSV) for ESD protection devices in 3D stacking integrated circuits

dc.contributor.authorChen, Shih-Hung
dc.contributor.authorThijs, Steven
dc.contributor.authorLinten, Dimitri
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-20T10:14:42Z
dc.date.available2021-10-20T10:14:42Z
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20441
dc.sourceIIOimport
dc.titleUtilizing Keep-Out Zone (KOZ) of Through Silicon Via (TSV) for ESD protection devices in 3D stacking integrated circuits
dc.typeProceedings paper
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorThijs, Steven
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecThijs, Steven::0000-0003-2889-8345
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.source.peerreviewyes
dc.source.beginpage391
dc.source.endpage399
dc.source.conferenceInternational ESD Workshop - IEW
dc.source.conferencedate14/05/2012
dc.source.conferencelocationOud-Turnhout Belgium
imec.availabilityPublished - imec


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